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1 4234b?scr?02/04 features smart card interface ? compliance with iso 7816, emv2000, gie-cb, gsm and whql standards card clock stop high or low for card power-down modes support synchronous cards with c4 and c8 contacts card detection and automatic de-activation sequence programmable activation sequence ? direct connection to the smart card logic level shifters short circuit current limitation 8kv+ esd protection (mil/std 883 class 3) ? programmable voltage 5v 5% at 65 ma (class a) 3v 0.2v at 65 ma (class b) 1.8v 0.14v at 40 ma ? low ripple noise: < 200 mv max versatile host interface ? icam (conditional access) compatible ? two wire interface (twi) link programmable address allow up to 8 devices ? programmable interrupt output ? automatic level shifter (1.6v to v cc ) reset output includes ? power-on reset (por) ? power-fail detector (pfd) high-efficiency step-up converter: 80 to 98% efficiency extended voltage operation: 2.85 to 5.5v low power consumption ? 1 ma maximum operating current ? 150 ma maximum in-rush current ?20 a typical power-down current (without smart card) 4 to 48 mhz clock input (7 mhz min for step-up converter) industrial temperature range: -40 to +85 c packages: so28 and qfn28 description the AT83C24 is a smart card reader interface ic for smart card reader/writer applica- tions such as eft/pos terminals and set top boxes. it enables the management of any type of smart card from any kind of host. up to 8 AT83C24 can be connected in parallel using the programmable twi address. its high efficiency dc/dc converter, low quiescent current in standby mode makes it particularly suited to low power and portable applications. the reduced bill of material allows reducing significantly the system cost. a sophisticated protection system guar- antees timely and controlled shutdown upon error conditions. smart card reader interface with power management AT83C24
2 AT83C24 4234b?scr?02/04 acronyms twi: two-wire interface por: power on reset pfd: power fail detect art: automatic reset transition atr: answer to reset block diagram pres/ int clk vss v cc crst cpres cio, cc4, cc8 cclk cvcc li reset voltage supervisor por/pfd twi controller clocks controller dc/dc converter analog drivers scl sda i/o, c4, c8 dvcc evcc a2, a1, a0, cmdvcc timer 16 bits main control & logic unit cvss
3 AT83C24 4234b?scr?02/04 pin description pinout (top view) AT83C24 28-pin soic pinout qfn28 pinout note: nc = not connected signals a1 a2 a0 1 evcc cclk crst scl vcc reset cvss cvcc i/o clk 2 3 4 5 6 7 8 9 10 28 27 26 25 24 23 22 21 20 19 li pres/int dvcc vss sda cpres 12 18 17 11 c8 cio c4 16 15 cc8 cmdvcc cc4 1 vss v cc cvss li 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 17 18 19 20 21 22 23 24 25 26 27 28 top view qfn 28 cio cc8 cvcc crst cpres cc4 cclk cmdvcc reset dvcc c8 clk pres/in t c4 /ck /ck /rst a0 /rst /3v /3v cvcc cvcc sda scl a1 a2 i/o evcc 13 14 nc nc nc nc table 1. ports description pad name pad internal power supply esd limits pad type description a2/ck- a1/rst- a0/3v evcc 3 kv i microcontroller interface function: twi bus slave address selection input. a2 and a1 pins are respectively connected to cclk and crst signals in ?transparent mode? (see transparent mode page 16). the slave address of the device is based on the value present on a2, a1, a0 on the rising edge of reset pin (see table 2). pres/int evcc 3 kv o open- drain microcontroller interface function: depending on it_sel value (see config4 register), pres/int outputs card presence status or interruptions (see interrupts page 9) an internal pull-up to evcc can be activated in the pad if necessary using int_pullup bit (config4 register). reset v cc 3 kv i/o open- drain microcontroller interface function: power-on reset a low level on this pin keeps the AT83C24 under reset even if applied on power-on. it also resets the AT83C24 if applied when the AT83C24 is running. asserting reset when the chip is in shut-down mode returns the chip to normal operation. AT83C24 is driving the reset pin low on power-on-reset or if power fail on v cc or dvcc (see powermon bit in config4 register), this can be used to reset or interrupt other devices. after reset, AT83C24 needs to be reconfigured before starting a new card session. sda v cc 3 kv i/o open- drain microcontroller interface function twi serial data scl v cc 3 kv i/o open- drain microcontroller interface function twi serial clock
4 AT83C24 4234b?scr?02/04 i/o evcc 3 kv i/o microcontroller interface function copy of card i/o and high level reference for evcc. the reset level on i/o must be maintained to 1 by the microcontroller. c4 evcc 3 kv i/o (pull-up) microcontroller interface function copy of card cc4. c8 evcc 3 kv i/o (pull-up) microcontroller interface function copy of card cc8. clk evcc 3 kv i microcontroller interface function master clock cio cvcc 8 kv+ i/o (pull-up) smart card interface function card i/o cc4 cvcc 8 kv+ i/o (pull-up) smart card interface function card c4 cc8 cvcc 8 kv+ i/o (pull-up) smart card interface function card c8 cpres v cc 8 kv+ i (pull-up) smart card interface function card presence an internal pull-up to vcc can be activated in the pad if necessary using pullup bit (config1 register). cclk cvcc 8 kv+ o smart card interface function card clock crst cvcc 8 kv+ o smart card interface function card reset cmdvcc evcc 3 kv+ i (pull-up) microcontroller interface function: activation/shutdown of the smart card interface. vcc 3 kv+ pwr supply voltage v cc is used to power the internal voltage regulators and i/o buffers. li 3 kv+ pwr dc/dc input li must be tied to v cc pin through an external coil (typically 4.7 h) and provides the current for the charge pump of the dc/dc converter. it may be directly connected to v cc if the step-up converter is not used (see stepreg in config4 register and see minimum vcc value in table 16 (class a) and table 17 (class b)). cvcc 8 kv+ pwr card supply voltage cvcc is the programmable voltage output for the card interface. it must be connected to an external decoupling capacitor. dvcc 3 kv+ pwr digital supply voltage is internally generated and used to supply the digital core. this pin has to be connected to an external capacitor of 100 nf and should not be connected to other devices. table 1. ports description (continued) pad name pad internal power supply esd limits pad type description
5 AT83C24 4234b?scr?02/04 evcc 3 kv+ pwr extra supply voltage (microcontroller power supply) evcc is used to supply the level shifters of host interface pins. evcc voltage can be supplied from the external evcc pin. it can also be generated internally by an automatic follow up of the logic high level on the i/o pin. in this configuration, connect a 100 nf + 100kohms in parallel between evcc pin and vss pin. cvss 8 kv+ gnd dc/dc ground cvss is used to sink high shunt currents from the external coil. vss gnd ground table 1. ports description (continued) pad name pad internal power supply esd limits pad type description
6 AT83C24 4234b?scr?02/04 operational modes twi bus control the atmel two-wire interface (twi) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 kbits per sec- ond, based on a byte-oriented transfer format. the twi-bus interface can be used: ? to configure the AT83C24 ? to select the operating mode of the card: 1.8v, 3v or 5v ? to configure the automatic activation sequence ? to start or stop sessions (activation and de-activation sequences) ? to initiate a warm reset ? to control the clock to the card in active mode ? to control the clock to the card in stand-by mode (stop low, stop high or running) ? to enter or leave the card stand-by or power-down modes ? to select the interface (connection to the host i/o/c4/c8) ? to request the status (card present or not, over-current and out of range supply voltage occurrence) ? to drive and monitor the card contacts by software ? to accurately measure the atr delay when automatic activation is used twi commands frame structure the structure of the twi bus data frames is made of one or a series of write and read commands completed by stop. write commands to the AT83C24 have the structure: address byte + command byte + data byte(s) read commands to the AT83C24 have the structure: address byte + data byte(s) the address byte is sampled on a2/ck, a1/rst, a0/3v after each reset (hard/soft/general call) but a2/ck, a1/rst, a0/3v can be used for transparent mode after the reset. figure 1. data transfer on twi bus sda scl start condition stop condition 1234 5 6 78 9 acknowledgement from slave adresse byte command and/or data
7 AT83C24 4234b?scr?02/04 address byte the first byte to send to the device is the address byte. the device controls if the hard- ware address (a2/ck, a1/rst, a0/3v pins on reset) corresponds to the address given in the address byte (a2, a1, a0 bits). if the level is not stable on a2/ck pin (or a1/rst pin, or a0/3v pin) at reset, the user has to manage the possible adress taken by the device. figure 2. address byte up to 8 devices can be connected on the same twi bus. each device is configured with a different combination on a2/ck, a1/rst, a0/3v pins. the address byte of each device for read/write operations are listed below. table 2. address byte values a2 (a2/ck pin) a1 (a1/rst pin) a0 (a0/3v pin) address byte for read command address byte for write command 0 0 0 0x41 0x40 0 0 1 0x43 0x42 0 1 0 0x45 0x44 0 1 1 0x47 0x46 1 0 0 0x49 0x48 1 0 1 0x4b 0x4a 1 1 0 0x4d 0x4c 1 1 1 0x4f 0x4e b7 b6 b5 b4 b3 b2 b1 b0 0 0 1 0a2 a1 a0 r/w slave address on 7 bits 1 for read command 0 for write command
8 AT83C24 4234b?scr?02/04 write commands the write commands are: 1. reset: initialize all the logic and the twi interface as after a power-up or power-fail reset. if the interface is activated, an emergency de-activation sequence is also performed. this is a one-byte command. 2. write config: configure the device according to the last six bits in the config0 register and to the following four bytes in config1, config2, config3 then config4 regis- ters. this is a five bytes command. figure 3. command byte format for write config0 command 3. write timer: program the 16-bit automatic reset transition timer with the following two bytes. this is a three bytes command. 4. write interface: program the interface. this is a one-byte command. the msb of the command byte is fixed at 0. 5. general call reset: a general call followed by the value 06h has the same effect as a reset command. table 3. write commands description address byte (see table 2) command byte data byte 1 data byte 2 data byte 3 data byte 4 1. reset 0100 xxx0 1111 1111 2. write config 0100 xxx0 (10 + config0 6 bits) config1 config2 config3 config4 3. write timer 0100 xxx0 1111 1100 timer1 timer0 4. write interface 0100 xxx0 (0+interface 7 bits) 5. general call reset 0000 0000 0000 0110 b7 b6 b5 b4 b3 b2 b1 1 x 0 x x x x config0 on 6 bits b0 x
9 AT83C24 4234b?scr?02/04 read command after the slave address has been configured, the read command allows to read one or several bytes in the following order: status, config0, config1, config2, config3, interface, timer1, timer0, capture1, capture0 ffh is completing the transfer if the microcontroller attempts to read beyond the last byte. note: flags are only reseted after the corresponding byte read has been acknowledged by the master. table 4. read command description interrupts the pres/int behavior depends on it_sel bit value (see config4 register). if it_sel= 0, the pres/int output is high by default. pres/int is driven low by at least one of the following event: ? insert bit set in config0 register (card insertion/extraction or bit set by software ) ? vcard_int bit set in status register (the dc/dc output voltage has settled) ? over-current detection on cvcc ? vcarderr bit set in config0 register (out of range voltage on cvcc or bit set by software) ? atrerr bit set in config0 register (no atr before the card clock counter overflows or bit set by software) if it_sel= 1 (for software compatibility with existing devices) the pres/int output is high to indicate a card is present and none of the following event has occured: ? over-current detection on cvcc ? vcarderr bit set in config0 register (out of range voltage on cvcc or bit set by software) ? atrerr bit set in config0 register (no atr before the card clock counter overflows or bit set by software) byte description byte value address byte 0100 xxx1 data byte 1 status data byte 2 config0 data byte 3 config1 data byte 4 config2 data byte 5 config3 data byte 6 config4 data byte 7 interface data byte 8 timer 1 data byte 9 timer 0 data byte 10 capture 1 data byte 11 capture 0 data byte 12 0xff
10 AT83C24 4234b?scr?02/04 several AT83C24 devices can share the same interrupt and the microcontroller can identify the interrupt sources by polling the status of the AT83C24 devices using twi commands. clock controller the clock controller outputs two clocks (as shown in figure 4 and figure 5): 1. a clock for the cclk: four different sources can be used: clk pin, dcclk sig- nal, cardck bit or a2/ck pin (in transparent mode). 2. a clock for the dc/dc block (dcclk signal): the dcclk frequency must be as close as possible to 3.68mhz. figure 4. clock block diagram with software activation (see activation sequence ) figure 5. clock block diagram with hardware activation (see activation sequence ) crst controller the crst output pin is driven by the a1/rst pin signal pin or by the cardrst bit value. this selection depends of the crst_sel bit value (see config4 register). dck[2:0] cks[2:0] clk a2/ck cclk dc/dc dcclk 0 1 ckstop bit cardck bit dck[2:0] cks[2:0] clk a2/ck cclk dc/dc dcclk 0 1 ckstop bit cardck bit cmdvcc a1/rst crst_sel bit hardware activation
11 AT83C24 4234b?scr?02/04 if the crst pin signal is driven by the cardrst bit value, two modes are available: if the art bit is reset, crst pin is driven by cardrst bit. if the art bit is set, crst pin is controlled and follows the ?automatic reset transition? (see figure 12). figure 6. crst block diagram figure 7. crst block diagram with hardware activation (cmdvcc pin used) cio, cc4, cc8 controller the cio, cc4, cc8 output pins are driven respectively by cardio, cardc4, cardc8 bits values or by i/o, c4, c8 sign al pins. this selection depends of the iodis bit value. if iodis is reset, data are bidirectional between respectively i/o, c4, c8 pins and cio, cc4, cc8 pins. a1/rst crst 0 1 crst_sel bit 0 1 art bit cardrst bit cardrst bit tb delay see fig 12 a1/rst crst 0 1 0 1 art bit cardrst bit crst_sel bit hardware activation cmdvcc
12 AT83C24 4234b?scr?02/04 figure 8. cio, cc4, cc8 block diagram io transceiver io and cio pins are linked together if iodis bit=0 in interface register. this is done automatically during an hardware activation. the iddle level is 1. the same behavior is applicable on c4/cc4 and c8/cc8 pins. card presence detection the card presence signal is connected on the cpres pin. the polarity of card presence contact is selected with t he carddet bit (see config1 register). a programmable fil- tering is controlled with the cds[2-0] bits. the internal pull-up on the cpres pin can be disconnected in order to reduce the con- sumption. an external pull-up must be connected to v cc . the pullup bit (see config1 register) controls this feature. if the card presence contact is connected to v cc , the internal pull-up must be discon- nected and an external pull-down must be connected to the cpres pin. an interrupt can be generated if a card is inserted or extracted (see interrupts). cio 0 1 0 1 cardio bit cc4 cc8 0 1 cardc8 bit iodis bit cardc4 bit i/o c4 c8
13 AT83C24 4234b?scr?02/04 figure 9. card presence input activation sequence hardware activation (dc/dc started with cmdvcc ) initial conditions: the crst_sel bit (see config4 register) must be set and cardrst bit (see interface register) must be cleared. the hardware activation sequence is started by hardware with cmdvcc pin going high to low. then cclk signal is automatically enabled when cvcc has settled to the programmed voltage (see electrical characteristics) and the level on a1/rst is 0. the cclk source can be dcclk signal, clk signal , a2/ck signals or cardck bit (see figures 5). crst signal must be controlled by hardware with the a1/rst pin. vcard[0-1] bits should not be set by software and cvcc is set according to the a0/3v pin: 5v (class a) if a0/3v is high and 3v (class b) is a0/3v is low. note: the card must be deactivated to change the voltage. pullup bit carddet bit = 1 closed = 0 open external pull-up resistor card presence contact = 1 no card if cpres = 0 = 0 no card if cpres = 1 cardin bit = 1 card inserted = 0 no card it controller cpres pres/int vcc/vss filtering cds[2-0] vcc vss/vcc int_pullup bit = 1 closed = 0 open evcc it_sel bit
14 AT83C24 4234b?scr?02/04 figure 10. activation sequence with cmdvcc software activation (dc/dc started with writing in vcard[1:0] bits) and art bit = 0 the activation sequence is controlled by software using twi commands, depending on the cards to support. for iso 7816 cards, the following sequence can be applied: 1. card voltage is set by software to the required value (vcard[1:0] bits in config0 register). this writing starts the dc/dc. 2. wait of the end of the dc/dc init with a polling on vcardok bit (status register) or wait for pres/int to go low if enabled (if it_sel bit = 0 in config4 register). when vcardok bit is set (by hardware), cardio bit should be set by software. 3. ckstop, iodis are programmed by software. ckstop bit is reset to have the clock running. iodis is reset to drive the i/o, c4, c8 pins and the cio,cc4, cc8 pins according to each other. 4. crst pin is controlled by software using cardrst bit (see interface register). cmdvcc a1/rst cclk cvcc crst
15 AT83C24 4234b?scr?02/04 figure 11. software activation without automatic control (art bit = 0) 1. it is assumed that initially vcard[1:0], cardck, cardio and cardrst bits are cleared, ckstop and iodis are set (those bits are further explained in the registers description) 2. the user should check the AT83C24 status and possibly resume the activation sequence if one twi transfer is not acknowledged during the activation sequence. software activation (dc/dc started with writing in vcard[1:0] bits) and art bit = 1 the following sequence can be applied: 1. card voltage is set by software to the required value (vcard[1:0] bits in config0 register). this writing starts the dc/dc. 2. wait of the end of the dc/dc init with a polling on vcardok bit (status register) or wait for pres/int to go low if enabled (if it_sel bit = 0 in config4 register). when vcardok bit is set (by hardware), cardio bit should be set by software. 3. ckstop, iodis are programmed by software. ckstop bit is reset to have the clock running. iodis is reset to drive the i/o, c4, c8 pins and the cio,cc4, cc8 pins according to each other. 4. cardrst bit (see interface register) is set by software. automatic reset transition description: a 16-bit counter starts when cardrst bit is set. it counts card clock cycles. the crst signal is set when the counter reaches the timer[1-0] value which corresponds to the ?tb? time (figure 5).the counter is reseted when the crst pin is released and it is stopped at the first start bit of the answer to request (atr) on cio pin. the cio pin is not checked during the first 200 clock cycles (time on figure 5). if the atr arrives before the counter reaches timer[1-0] value, the activation sequence fails, the crst signal is not set and the capture[1-0] register contains the value of the counter at the arrival of the atr. cvcc crst cclk cio 2 4 3 1 atr
16 AT83C24 4234b?scr?02/04 if the atr arrives after the rising edge on crst pin and before the card clock counter overflows (65535 clock cycles), the activation sequence completes. the capture[1-0] register contains the value of the counter at the arrival of the atr (tc time on figure 12). figure 12. software activation with art bit = 1 iso 7816 constraints: ta = 200 card clock cycles 400 card clock cycles< = tb 400 card clock cycles< = tc < = 40000 card clock cycles note: timer[1-0] reset value is 400. deactivation sequence the card automatic deactivation is triggered when one the following condition occurs: icarderr bit is set by hardware vcarderr bit is set by hardware (or by software) insert is set and cardin is cleared (card extraction) shutdown is set by software cmdvcc goes from low to high power fail on vcc (see powermon bit in config4 register) reset pin going low it is a self-timed sequence which cannot be interrupted when started (see figure 13). each step is separated by a delay based on td equal to 8 periods of the dc/dc clock, typically 2 to 2.4 s: 1. t0: cardrst is cleared, shutdown bit set. 2. t0 + 5 x td:cardck is cleared, ckstop, cardio and iodis are set. 3. t0 + 6 x td: cardio is cleared. cvcc crst cclk tc tb ta cio cardrst bit set 1 2 3 4
17 AT83C24 4234b?scr?02/04 4. t0 + 7 x td: vcard[1-0] = 00. figure 13. deactivation sequence notes: 1. setting icarderr by software does not trigger a deactivation. vcarderr can be used to deactivate the card by software. transparent mode if the microcontroller outputs iso 7816 signals, a transparent mode allows to connect rst/clk and i/o/c4/c8 signals after an electrical level control. the AT83C24 level shifters adapt the card signals to the smart card voltage selection. the crst and cclk microcontroller signals can be respectively connected to the a1/rst and a2/ck pins. the crst_sel bit (in config4 register) selects standard or transparent configuration for the crst pin. cks in config2 allows to select standard or transparent configura- tion for the cclk pin. so cclk and crst are independent. a2/ck to a0/3v inputs always give the twi address at reset. the a0/3v pin can be used for twi addressing and easily connect two AT83C24 devices on the same twi bus. if a2/ck to a0/3v are tied to the host microcontroller and their reset values are unknown, a general call on the twi bus allows to reset all the AT83C24 devices and set their address after a2/ck to a0/3v are fixed. cvcc crst cclk cio, 5 x td td td cc4, cc8
18 AT83C24 4234b?scr?02/04 figure 14. transparent mode description power modes two power-down modes are available to re duce the AT83C24 power consumption (see stutdown bit in config1 register and lp bits in config3 register). to enter in the mode number 4 (see table 5), the sequence is the following: ? first select the low-power mode by setting the lp bit ? the activation of the shutdown bit can then be done. the AT83C24 exits power-down if a software/hardware reset is done or if shutdown bit is cleared. the AT83C24 is then active immediately. either a hardware reset or a twi command clearing the shutdown bit can cause an exit from power-down. the internal regist ers retain their value during the shutdown mode. in power-down mode, the device is sleeping and waiting for a wake up condition. to reduce power consumption, the user should stop the clock on the clk input after setting the shutdown bit. the clock can be enabled again just before exiting shut- down (at least 10 s before a start bit on sda). cclk crst cio i/o a2/ck a1/rst AT83C24 smart card crst cclk cc4 microcontroller cc8 cio c4 c8 cc4 cc8 table 5. power modes description mode number shutdown bit lp bit result typical supply current description 1 0 x no action tbd ma step up mode: vcc = 2.85v, cvcc = 5v, icvcc = 65ma 2 0 x no action tbd ma regulator mode: vcc = 5.2v, cvcc = 5v, icvcc = 65ma 3 1 0 shutdown mode 90 a the twi interface of the AT83C24 is active but its analog blocs are switched off to reduce the consumption 4 1 1 shutdown mode with low power mode 30 a pulsed mode of the internal 3v logic regulator
19 AT83C24 4234b?scr?02/04 power monitoring the AT83C24 needs only one power supply to run: vcc. if the microcontroller outputs signals with a different electrical level, the host positive supply is connected to evcc. evcc and vcc pins can be connected together if they have the same voltage. if evcc and vcc have different electrical levels: the evcc pin and reset pin should be connected with a resistor bridge. reset pin high level must be higher than vih (see table 15). when evcc drops, reset pin level drops too. a deactivation sequence starts if a card was active. then the AT83C24 resets if r eset pin stays low. vcc monitoring: the AT83C24 integrates an internal 3v regulator to feed its logic from the vcc sup- ply. the bit powermon allows the user to select if the internal pfd monitors vcc or the internal regulated 3v. if the pfd monitors vcc (powermon bit=0), a deacti- vation is performed if vcc falls below vpfdp (see vpfdp value in the datasheet). same deactivation is performed if the internal 3v falls below vpfdp and power- mon bit = 1
20 AT83C24 4234b?scr?02/04 registers table 6. config0 (config byte 0) 7 6 5 4 3 2 1 0 1 0 atrerr insert icarderr vcarderr vcard1 vcard0 bit number bit mnemonic description 7-6 1-0 these bits cannot be programmed and are read as 1-0. 5 atrerr answer to reset interrupt this bit is set when the card clock counter overflows (no falling edge on cio is received before the overflow of the card clock counter). this bit is cleared by hardware when this register is read. it can be set by software for test purpose. the reset value is 0. 4 insert card insertion interrupt this bit is set when a card is inserted or extracted: a change in cardin value filtered according to cds[2-0]. it can be set by software for test purpose. this bit is cleared by hardware when this register is read. it cannot be cleared by software. the reset value is 0. 3 icarderr card over current interrupt this bit is set when an over current is detected on cvcc. it can be set by software for test purpose (no card deactivation is performed). this bit is cleared by hardware when this register is read. it cannot be cleared by software. the reset value is 0. 2 vcarderr card out of range voltage interrupt this bit is set when the output voltage goes out of the voltage range specified by vcard field. it can be set by software for test purpose and deactivate the card. this bit is cleared by hardware when this register is read. it cannot be cleared by software. the reset value is 0. 1-0 vcard[1:0] card voltage selection vcard[1:0] = 00: 0v vcard[1:0] = 01: 1.8v vcard[1:0] = 10: 3v vcard[1:0] = 11: 5v vcard[1:0] writing to 1.8v, 3v, 5v starts the dc/dc if a card is detected. vcard[1:0] writing to 0 stops the dc/dc. no card deactivation is performed when the voltage is changed between 1.8v, 3v or 5v. the microcontroller should deactivate the card before changing the voltage. the reset value is 00.
21 AT83C24 4234b?scr?02/04 table 7. config 1 (config byte 1) 7 6 5 4 3 2 1 0 0 art shutdown carddet pullup cds2 cds1 cds0 bit number bit mnemonic description 7 0 this bit should not be set and is read as 0. 6 art automatic reset transition set this bit to have the crst pin changed according to activation sequence. clear this bit to have the crst pin immediately following the value programmed in cardrst. the reset value is 0. 5 shutdown shutdown set this bit to reduce the power consumption. an automatic de-activation sequence will be done. clear this bit to enable vcard[1:0] selection. the reset value is 0. 4 carddet card presence detection polarity set this bit to indicate the card presence detector is closed when no card is inserted (cpres is low). clear this bit to indicate the card presence detector is open when no card is inserted (cpres is high). the reset value is 0. 3 pullup pull-up enable set this bit to enable the internal pull-up on the cpres pin. this allows to minimize the number of external components. clear this bit to disable the internal pull-up and minimize the power consumption when the card detection contact is on. then an external pull-up must be connected to v cc (typically a 1 m ? resistor). the reset value is 1. 2-0 cds[2:0] card detection filtering cpres is sampled by the master clock provided on clk input. a change on cpres is detected after: cds[2-0] = 0: 0 sample (1) cds[2-0] = 1: 4 identical samples cds [2-0] = 2: 8 identical samples (reset value) cds[2-0] = 3: 16 identical samples cds[2-0] = 4: 32 identical samples cds[2-0] = 5: 64 identical samples cds[2-0] = 6: 128 identical samples cds[2-0] = 7: 256 identical samples the reset value is 2. note: 1. when cds[2-0] = 0 and it_sel = 0, pres/int = 1 when no card is present and pres/int = 0 when a card is inserted even if clk is stopped. this can be used to wake up the external microcontroller and restart clk when a card is inserted in the AT83C24. if cds[2-0] = 0, it_sel = 1 and clk is stopped, a card insertion or extraction has no effect on pres/int pin.
22 AT83C24 4234b?scr?02/04 notes: 1. when this field is changed a special logic insures no glitch occurs on the cclk pin and actual configuration changes can be delayed by half a period to two periods of cclk. 2. cclk must be stopped with ckstop bit before switching from cks = (0, 1, 2, 3, 6, 7) to cks = (4, 5) or vice versa. 3. when dck = 0, a change on cks as no effect. table 8. config2 (config byte 2) 7 6 5 4 3 2 1 0 0 dck2 dck1 dck0 0 cks2 cks1 cks0 bit number bit mnemonic description 7 0 this bit should not be set and is read as 0. 6-4 dck[2:0] dc/dc clock prescaler factor dcclk is the dc/dc clock. it is the division of clk input by dck prescaler. dck = 0: prescaler factor equals 1 (clk = 3.5 to 4.6mhz) dck [2:0] = 1: prescaler factor equals 2 (clk = 7 to 9.2mhz) dck [2:0] = 2: prescaler factor equals 4 (clk = 14 to 18.4 mhz) dck [2:0] = 3: prescaler factor equals 6 (clk = 21 to 27.6 mhz) dck [2:0] = 4: prescaler factor equals 8 (clk = 28 to 34.8 mhz) dck [2:0] = 5: prescaler factor equals 10 (clk = 35 to 43 mhz) dck [2:0] = 6: prescaler factor equals 12 (clk = 43.1 to 48 mhz) dck [2:0] = 7: reserved the reset value is 1. dcclk must be as close as possible to 3.68 mhz with a duty cycle of 50%. dcclk must be programmed before to start the dc/dc. the other values of clk are not allowed. dck has to be properly configured before resetting the stepreg bit. 3 0 this bit should not be set and is read as 0. 2-0 cks[2:0] card clock prescaler factor cks [2:0] = 0: cclk = clk (then the maximum frequency on clk is 24 mhz) cks [2:0] = 1: cclk = dcclk (dc/dc clock) cks [2:0] = 2: cclk = dcclk / 2 cks [2:0] = 3: cclk = dcclk / 4 cks [2:0] = 4: cclk = a2 cks [2:0] = 5: cclk = a2 / 2 cks [2:0] = 6: cclk = clk / 2 cks [2:0] = 7: cclk = clk / 4 the reset value is 0.
23 AT83C24 4234b?scr?02/04 table 9. config3 (config byte 3) 7 6 5 4 3 2 1 0 eauto vext1 vext0 iccadj lp 0 0 0 bit number bit mnemonic description 7-5 eauto vext1 vext0 evcc voltage configuration: eauto vext1 vext0 0 0 0 evcc = 0 the regulator is switched off. 0 0 1evcc = 2.3v 0 1 0 evcc = 1.8v 0 1 1 evcc = 2.7v 1 x x evcc voltage is the level detected on i/o input pin. if evcc is supplied from the external evcc pin, the user can switch off the internal evcc regulator to decrease the consumption. if evcc is switched off, and no external evcc is supplied, the AT83C24 is inactive until a hardware reset is done. the reset value is 100. 4 iccadj ci cc overflow adjust this bit controls the dc/dc sensitivity to any overflow current. set this bit to decrease the dc/dc sensitivity (ci cc_ovf is increased by about 20%). clear this bit to have a normal configuration. the reset value is 0. 3 lp low-power mode set this bit to enable low-power mode during shutdown mode (pulsed mode activated). clear this bit to disable low-power mode during shutdown mode. the activation reference is the following: first select the low-power mode by setting lp bit. the activation of shutdown bit can then be done. this bit as no effect when shutdown bit is cleared. the reset value is 0. 2 0 this bit should not be set and is read as 0. 1 0 this bit should not be set and is read as 0. 0 0 this bit should not be set and is read as 0.
24 AT83C24 4234b?scr?02/04 table 10. config4 (config byte 4) 7 6 5 4 3 2 1 0 0 0 0 stepreg int_pullup powermon it_sel crst_sel bit number bit mnemonic description 7-5 0-0-0 these bits should not be set and are read as 0. 4 stepreg step regulator mode clear this bit to enable the automatic step-up converter (cvcc is stable even if vcc is not higher than cvcc). set this bit to permanently disable the step-up converter (cvcc is stable only if vcc is sufficiently higher than cvcc). the reset value is 0. this bit must always be set if no external self is used 3 int_pullup internal pull-up set this bit to activate the internal pull-up (connected internally to evcc) on pres/int pin. clear this bit to deactivate the internal pull-up. the reset value is 0. 2 powermon power monitor set this bit so that the internal power monitor checks the digital supply voltage (dvcc) of the AT83C24. clear this bit so that the internal power monitor checks the v cc of the AT83C24. the reset value is 0. 1 it_sel interrupt select set this bit to disable insert and vcard_int interrupts. then pres/int is driven high when a card is present and no error is detected. clear this bit to have all the interrupt sources enabled and active low. then pres/int is an open-drain output with a programmable pull-up (see int_pullup). the reset value is 0. 0 crst_sel card reset selection set this bit to have the crst pin driven by hardware through the a1 pin. clear this bit to have the crst pin driven by software through the cardrst bit. the reset value is 0.
25 AT83C24 4234b?scr?02/04 table 11. interface (interface byte) 7 6 5 4 3 2 1 0 0 iodis ckstop cardrst cardc8 cardc4 cardck cardio bit number bit mnemonic description 7 0 this bit cannot be programmed and is read as 0. 6 iodis card i/o isolation set this bit to drive the cio, cc4, cc8 pins according to cardio, cardc4, cardc8 respectively and to put i/o, c4, c8 in hi-z. this can be used to have the i/o, and c4 and c8 pins of the host communicating with another AT83C24 interface, while cio, cc4 and cc8 are driven by software (or if the card is in standby or power-down modes). clear this bit to drive the i/o/cio, c4/cc4 and c8/cc8 pins according to each other. this can be used to activate asynchronous cards. the reset value is 1. 5 ckstop card clock stop set this bit to stop cclk according to cardck. this can be used to set asynchronous cards in power-down mode (gsm) or to drive cclk by software. clear this bit to have cclk running according to cks. this can be used to activate asynchronous cards. note: when this bit is changed a special logic ensures that no glitch occurs on the cclk pin and actual con- figuration changes can be delayed by half a period to two periods of cclk. the reset value is 1. 4 cardrst card reset set this bit to enter a reset sequence according to art bit value. clear this bit to drive a low level on the crst pin. the reset value is 0. 3 cardc8 card c8 set this bit to drive the cc8 pin high with the on-chip pull-up (according to iodis bit value). the pin can then be an input (read in status register). clear this bit to drive a low level on the cc8 pin (according to iodis bit value). the reset value is 0. 2 cardc4 card c4 set this bit to drive the cc4 pin high with the on-chip pull-up (according to iodis bit value). the pin can then be an input (read in status register). clear this bit to drive a low level on the cc4 pin (according to iodis bit value). the reset value is 0. 1 cardck card clock set this bit to set a high level on the cclk pin (according to ckstop bit value). clear this bit to drive a low level on the cclk pin. the reset value is 0. 0 cardio card i/o set this bit to drive the cio pin high with the on-chip pull-up (according to iodis bit value). the pin can then be an input (read in status register). clear this bit to drive a low level on the cio pin (according to iodis bit value). the reset value is 0.
26 AT83C24 4234b?scr?02/04 reset value = 0x00000001 table 12. status (status byte) 7 6 5 4 3 2 1 0 cc8 cc4 cardin vcardok 0 vcard_int crst cio bit number bit mnemonic description 7 cc8 card cc8 this bit provides the actual level on the cc8 pin when read. the reset value is 0. 6 cc4 card cc4 this bit provides the actual level on the cc4 pin when read. the reset value is 0. 5 cardin card presence status this bit is set when a card is detected. it is cleared otherwise. 4 vcard_ok card voltage status this bit is set by the dcdc when the output voltage remains within the voltage range specified by vcard[1:0] bits. it is cleared otherwise. the reset value is 0. 3 0 this bit should not be set and is read as 0. 2 vcard_int card voltage interrupt this bit is set when vcard_ok bit is set. this bit is cleared when read by the microcontroller. the reset value is 0. 1 crst card rst this bit provides the actual level on the crst pin when read. the reset value is 0. 0 cio card i/o this bit provides the actual level on the cio pin when read. the reset value is 0. table 13. timer (timer msb) 7 6 5 4 3 2 1 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit number bit mnemonic description 7 - 0 bits 15 - 8 timer msb (bits 15 to 8)
27 AT83C24 4234b?scr?02/04 reset value = 0x10010000 reset value = 0x00000000 reset value = 0x00000000 table 14. timer (timer lsb) 7 6 5 4 3 2 1 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit number bit mnemonic description 7 - 0 bits 7 - 0 timer lsb (bits 7to 0) table 15. capture (capture msb) 7 6 5 4 3 2 1 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit number bit mnemonic description 7 - 0 bits 15 - 8 see automatic activation sequence. table 16. capture (capture lsb) 7 6 5 4 3 2 1 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit number bit mnemonic description 7 - 0 bits 7 - 0 see automatic activation sequence (page 7).
28 AT83C24 4234b?scr?02/04 electrical characteristics absolute maximum ratings * ac/dc parameters evcc connected to host power supply: from 1.6v to 5.5v. t a = -40 c to +85 c; v ss = 0v; v cc = 2.85v to 5.5v. class a card supplied with cvcc = 4.75 to 5.25v for AT83C24tv class a card supplied with cvcc = 4.6 to 5.25v for AT83C24 class b card supplied with cvcc = 2.8v to 3.2v class 1.8v: card supplied with cvcc = 1.68v to 1.92v ambient temperature under bias: .....................-40 c to 85 c storage temperature: ................................... -65 c to +150 c voltage on v cc : .......................................... v ss -0.5v to +6.0v voltage on any pin: ............................. v ss -0.5v to v cc + 0.5v power dissipation: .......................................................... 1.5w thermal resistor of qfn package..................................35c/w thermal resistor of soic package.................................48c/w *notice: stresses at or above those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions may affect device reliability. power dissipation value is based on the maxi- mum allowable die temperature and the thermal resistance of the package. table 17. core parameters ( v cc ) symbol parameter min typ max unit test conditions v pfdp power fail high level threshold 2.4 2.5 2.6 v v pfdm power fail low level threshold 2.25 2.35 2.45 v t rise, t fall v dd rise and fall time 1 s 1 hour table 18. host interface parameters (i/o, c4, c8, clk, a2, a1, a0, cmdvcc , pres/int ) symbol parameter min ty p max unit test conditions v il input low-voltage -0.5 0.3 x evcc 0.25 x evcc v evcc from 2.7v to v cc evcc from 1.6 to 2.7v v ih input high voltage 0.7 x evcc evcc + 0.5 v evcc from 1.6v to v cc v ol output low-voltage (i/o, c4, c8, pres/int) 0.05 0.4 v v i ol = -100 a i ol = -1.2 ma v oh output high voltage (i/o, c4, c8, pres/int) 0.8 x evcc evcc v evcc from 1.6v to v cc i oh = 100 a ei cc extra supply current +3 ma c l = 100 nf r pres/int pres/int weak pull-up output current 300 330 360 ? short to vss int_pullup = 0: internal pull-up active.
29 AT83C24 4234b?scr?02/04 notes: 1. capacitor: x7r type, max esr value is 250 m ? , inductor = 4.7 h typ. ev cc extra supply voltage vpeak - 10 mv vpeak vpeak + 25 mv v c l = 100 nf, eicc = +3 ma vpeak on i/o from 1.6v to v cc min duration tdb, max period tbd table 18. host interface parameters (i/o, c4, c8, clk, a2, a1, a0, cmdvcc , pres/int ) (continued) symbol parameter min typ max unit test conditions table 19. host interface dc parameters (scl, sda, reset) symbol parameter min typ max unit test conditions v il input low-voltage -0.5 0.3 x v cc v v ih input high voltage 0.7 x v cc v cc + 0.5 v v ol output low-voltage 0.4 v i ol = -3 ma v hist input trigger hysteresis 0.1 x v cc table 20. smart card class a dc parameters symbol parameter min typ max unit test conditions ci cc card supply current capability 65 65 65 65 ma v cc = 5.5v, stepreg = 0 v cc = 3v, stepreg = 0 v cc = 2.85v, stepreg = 0 v cc = 5.35v, stepreg = 1 ci cc _ovf card supply current overflow: iccadj = 0 (reset value) iccadj = 1 0.07 0.07 0.12 0.13 0.13 0.15 a v cc from 3.0 to 5.5v ripple on cvcc 60 200 mv 0 < icard < 65 ma spikes on cvcc 4.6 5.3 v max. charge 40 na.s max. duration 400 ns max. icard variation 200 ma vcardok up vcardok high level threshold 4.8 4.9 v vcardok down vcardok low level threshold 4.6 4.8 v t vhl cvcc valid to 0 250 500 250 750 s icard = 0, v cc = 2.85v cvcc = 4.5v to 0.5v c l = 3.3 f (see note 1) c l = 10 f (see note 1) t vlh cvcc 0 to valid tbd tbd tbd tbd tbd tbd s icard = 65 ma AT83C24tv icard = 60 ma AT83C24 icard = 0. c l = 10 f (see note) cvcc = 0 to vcardok
30 AT83C24 4234b?scr?02/04 notes: 1. capacitor: x7r type, max esr value is 250 m ? , inductor = 4.7 h typ. table 21. smart card class b dc parameters symbol parameter min ty p max unit test conditions ci cc card supply current capability 65 65 65 65 ma v cc = 5.5v, stepreg = 0 v cc = 3v, stepreg = 0 v cc = 2.85v, stepreg = 0 v cc = 3.25v, stepreg = 1 ci cc _ovf card supply current overflow: iccadj = 0 (reset value) iccadj = 1 0.07 0.07 0.13 0.14 0.14 0.16 a v cc from 3.0 to 5.5v ripple on cvcc 60 200 mv 0 AT83C24tv icard = 60 ma AT83C24 icard = 0. c l = 10 f (see note) cvcc = 0 to vcardok
31 AT83C24 4234b?scr?02/04 note: capacitor = 10 f, x7r type, max esr value is 250 m ? , inductor = 4.7 h typ. table 22. smart card 1.8v dc parameters symbol parameter min typ max unit test conditions ci cc card supply current capability 20 20 20 15 ma v cc = 5.5v v cc = 4v v cc = 3v v cc = 2.85v ci cc _ovf card supply current overflow: iccadj = 0 (reset value) iccadj = 1 tbd tbd tbd tbd tbd tbd a spikes on cvcc tbd tbd v tbd vcardok up vcardok high level threshold tbd tbd v vcardok down vcardok low level threshold tbd tbd v t vhl cvcc valid to 0 tbd s icard = 0, c l = 10 f (1) cvcc = 1.8v to 0.4v t vlh cvcc 0 to valid tbd tbd tbd tbd s r l = 90 ? r l = 0 icard = 0, c l = 10 f (1) cvcc = 0.4 to vcardok table 23. smart card clock dc parameters (cclk pin) symbol parameter min typ max unit test conditions v ol output low-voltage 0 0.4 v i ol = -200 a class a&b&1.8v v oh output high voltage cvcc - 0.45 tbd cvcc tbd v i oh = +200 a class a&b class 1.8v i os short circuit current -30 30 ma short to gnd or cvcc t r t f rise and fall time 16 22.5 tbd ns c l = 30 pf class a c l = 30 pf class b class 1.8v rise and fall slew rate 0.2 0.12 tbd v/ns class a cclk from 0.5 to 4.2v class b cclk from 0.5 to 0.85 x cvcc class 1.8v low level voltage stability -0.25 tbd 0.5 tbd v class a&b class 1.8v
32 AT83C24 4234b?scr?02/04 high level voltage stability cvcc-0.5 cvcc-0.4 tbd cvcc+0.25 cvcc+0.25 tbd v cvcc = class a cvcc = class b class 1.8v table 23. smart card clock dc parameters (cclk pin) (continued) symbol parameter min typ max unit test conditions table 24. smart card i/o dc parameters (cio, cc4, cc8 pins) symbol parameter min typ max unit test conditions v il input low-voltage -0.3v 0.8 v i il = 500 a i il input low current 700 a cvcc = class a&b&1.8 v ih input high voltage 0.6 x cvcc 0.7 x cvcc cvcc cvcc v cvcc = class a cvcc = class b & 1.8v i ih input high current -20 +20 a v ol output low-voltage 0 0.45 0.3 tbd v i ol = -1 ma class a i ol = -1 ma class b i ol = -1 ma class 1.8v v oh output high voltage 0.75 x cvcc 0.9 x cvcc cvcc cvcc v i oh = 40 a class a&b&1.8v i oh = 0 a, class a&b i os output short circuit current -15 +15 ma short to gnd or cvcc low level voltage stability -0.25 -0.25 tbd 0.6 0.4 tbd v class a class b class 1.8v high level voltage stability cvcc-0.5 cvcc+0.25 v cvcc = class a&b&1.8 t r t f rise and fall time 0.1 s c l = 65 pf class a: 0.6v <--> 0.7 x cvcc class b & 1.8v: 0.4v <--> 0.7 x cvcc table 25. smart card rst dc parameters (crst pin) symbol parameter min typ max unit test conditions v ol output low-voltage 0 0 0.12 x cvcc 0.4 v i ol = -20 a class a&b&1.8v i ol = -200 a class a&b&1.8v v oh output high voltage cvcc - 0.45 cvcc v i oh = 200 a class a&b&1.8v i os output high current -15 +15 ma short to gnd or cvcc t r t f rise and fall time 0.1 s c l = 30pf low level voltage stability -0.25 0.5v 0.3v tbd v class a class b class 1.8v
33 AT83C24 4234b?scr?02/04 high level voltage stability cvcc-0.5 cvcc-0.4 tbd cvcc+0.25 v class a class b class 1.8v table 25. smart card rst dc parameters (crst pin) (continued) symbol parameter min typ max unit test conditions table 26. card presence dc parameters symbol parameter min typ max unit test conditions r cpres cpres weak pull-up output current 300 330 360 ? short to vss pullup = 1: internal pull-up active
34 AT83C24 4234b?scr?02/04 typical application figure 1. typical standard mode application diagram note: 1. the external resistor on i/o can be removed if the c51 pin has an internal resistor. 100nf xtal1 xtal2 + 10uf c51 vss vss 100nf vss c1 c2 c3 4.7h vss vss card 0 pres/int clk vss v cc crst cpres cio, cc4, cc8 cclk cvcc li cvss AT83C24 scl sda i/o, c4, c8 pres/int clk vss v cc crst cpres cio, cc4, cc8 cclk cvcc li cvss AT83C24 scl sda i/o, c4, c8 pres/int clk vss v cc crst cpres cio, cc4, cc8 cclk cvcc li cvss AT83C24 scl sda i/o, c4, c8 card 1 card n v cc microcontroller twi int0 px.y 100nf cvss c4 4.7h v cc 100nf cvss c7 4.7h v cc l1 l2 l reset rst v cc 4 to 48 mhz reset reset v cc vss v cc vss v cc a2 a1 a0 a2 a1 a0 a2 a1 a0 evcc evcc evcc evcc evcc evcc vss dvcc vss dvcc vss dvcc 100nf vss c5 + 10uf vss c 6 100nf vss c8 + 10uf vss c 9 100nf 100nf 100nf note vcc
ordering information note: 1. enhanced ac/dc parameters. part number supply voltage temperature range package packing product marking AT83C24-tisil 2.85v to 5.5v industrial so28 stick AT83C24 AT83C24-tiril 2.85v to 5.5v industrial so28 tape&reel AT83C24 AT83C24-prtil 2.85v to 5.5v industrial qfn28 tray AT83C24 AT83C24-prril 2.85v to 5.5v industrial qfn28 tape&reel AT83C24 AT83C24tv-tisil (1) 2.85v to 5.5v industrial so28 stick AT83C24 AT83C24tv-tiril (1) 2.85v to 5.5v industrial so28 tape&reel AT83C24 AT83C24tv-prtil (1) 2.85v to 5.5v industrial qfn28 tray AT83C24 AT83C24tv-prril (1) 2.85v to 5.5v industrial qfn28 tape&reel AT83C24
36 AT83C24 4234b?scr?02/04 package drawings qfn28
37 AT83C24 4234b?scr?02/04 so28
38 AT83C24 4234b?scr?02/04 datasheet change log changes from 4234a- 05/03 to 4234b-02/04 1. addition of crst, cio, cclk controllers descriptions, page 10. 2. update of hardware\software activation description, page 13. 3. suppression of low voltage regulator mode for power down modes, page 18. 4. modification of clock values in config2 regsiter, page 22. 5. addition of a point on qfn pinout view, page2. 6. update of electrical characteristics, page 28.
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